Semiconductor chips need to be packaged, and the semiconductor chips may be protected with packaging technology, thereby preventing the semiconductor chips from being polluted by an external environment. In addition, circuit interfaces in the semiconductor chips may also be leaded out with the packaging technology, thereby facilitating connection between the semiconductor chips and other circuits.
The existing mainstream packaging technology is wafer level chip size packaging (WLCSP) technology, in which, a whole wafer is packaged and tested, and then the wafer is cut to obtain a single finished chip. A size of the single finished chip packaged with the packaging technology is the same as that of a single die, which meets market requirements of being lighter, smaller, shorter, thinner and cheaper for microelectronic products. The wafer level chip size packaging technology is a hot topic and a future development trend in the current packaging field.
Reference is made to FIG. 1, which shows a wafer 1′. The wafer 1′ is a wafer level semiconductor chip with a size such as 8 inches, 12 inches or other size, and the size of the wafer 1′ is not limited herein. Multiple dies 11′ are arranged in an array on the wafer 1′, and the dies 11′ are semiconductor chips having image sensors. Reference is made to FIG. 2, which is a schematic diagram of a structure obtained after a protective substrate 2′ is aligned and laminated with the wafer 1′. A shape and a size of the protective substrate 2′ are the same as those of the wafer 1′. In the embodiment, the protective substrate 2′ is optical glass with high transmittance, and multiple support units are arranged in an array on the protective substrate 2′. The wafer 1′ and the protective substrate 2′ are aligned and laminated by coating adhesive on the top of the support units. The support units are arranged between the wafer 1′ and the protective substrate 2′, to form a certain gap between the wafer 1′ and the protective substrate 2′. Each of the support units corresponds to one die 11′. The die 11′ has a functional region 111′, which is enclosed by the support unit. In general, the support unit has a double-layer structure or a multi-layer structure, thereby isolating and protecting the functional region 111′, forming a gap between the wafer 1′ and the protective substrate 2′ and providing an enough support force. The support unit includes an inner support member 211′ and an outer support member 212′. In a case that the wafer 1′ and the protective substrate 2′ are laminated together, a closed accommodating cavity 213′ is formed among the inner support member 211′, the wafer 1′ and the protective substrate 2′.